Project X-Ray
Project X-Ray

# clb-ram Fuzzer

<table border=”1” class=”docutils”> <thead> <tr> <th>Primitive</th> <th>RAM</th> <th>SMALL</th> <th>SRL</th> </tr> </thead> <tbody> <tr> <td>LUT6</td> <td></td> <td></td> <td></td> </tr> <tr> <td>SRL16E</td> <td></td> <td>X</td> <td>X</td> </tr> <tr> <td>SRLC32E</td> <td></td> <td></td> <td>X</td> </tr> <tr> <td>RAM32X1S</td> <td>X</td> <td>X</td> <td></td> </tr> <tr> <td>RAM64X1S</td> <td>X</td> <td></td> <td></td> </tr> <tr> <td>RAM32M</td> <td>X</td> <td>X</td> <td></td> </tr> <tr> <td>RAM32X1D</td> <td>X</td> <td>X</td> <td></td> </tr> <tr> <td>RAM64M</td> <td>X</td> <td></td> <td></td> </tr> <tr> <td>RAM64X1D</td> <td>X</td> <td></td> <td></td> </tr> <tr> <td>RAM128X1D</td> <td>X</td> <td></td> <td></td> </tr> <tr> <td>RAM256X1S</td> <td>X</td> <td></td> <td></td> </tr> <tr> <td>RAM128X1S</td> <td>X</td> <td></td> <td></td> </tr> </tbody> </table>

## NLUT.RAM

Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.

## NLUT.SMALL

Seems to be set on smaller primitives.

## NLUT.SRL

Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E

## WA7USED

Set to 1 to propagate CLB’s CX input to WA7

## WA8USED

Set to 1 to propagate CLB’s BX input to WA8

## WEMUX.CE

<table border=”1” class=”docutils”> <thead> <tr> <th>WEMUX.CE</th> <th>CLB RAM write enable</th> </tr> </thead> <tbody> <tr> <td>0</td> <td>CLB WE input</td> </tr> <tr> <td>1</td> <td>CLB CE input</td> </tr> </tbody> </table>