Some PIPs are not “real”, in the sense that no bit pattern in the bit-stream correspond to the PIP being used. This is the case for all the PIPs in the switchbox in a CLB tile (ex: CLBLM_L_INTER): They either correspond to buffers that are always on (i.e. 1:1 connections such as CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0), or they correspond to permutations of LUT input signals, which is handled by changing the LUT init value accordingly, or they are used to “connect” two signals that are driven by the same signal from within the CLB.
FIXME: Check the above is true.
The bit switchbox in an INTs tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits.
Regular PIPs correspond to a bit pattern that is present in the bit stream when the PIP is used in the current design. There is a block of up to 10-ish bits for each destination signal. For each configuration (i.e. source net that can drive the destination) there is a pair of bits that is set.
FIXME: Check if the above is true for PIPs outside of the INT switch box.
For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an INT_L <INT>`s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db for a complete list of bit pattern for configuring PIPs.
The default state for a net is to be driven high. The PIPs that drive a net from VCC_WIRE correspond to the “empty configuration” with no bits set.