tilegrid file

The tilegrid.json is a list of all tiles in the device. This information is used at various stages of the flow i.e. for database generation or creating a bitstream. The most important parts of the file are related to frame addressing within the bitstream, grid and clock region location, list of underlying sites, or the type of the tile itself.

Before diving into this section, it is advised to familiarize yourself with the 7-Series Bitstream Format chapter and Configuration chapter.

File format

The file consists of the entries describing every tile in the FPGA chip. The file is of the form:

{
    "<TILE_NAME>": {
        "bits": {
            "<CONFIGURATION_BUS>": {
                "baseaddr": "<BASE_ADDR>,
                "frames": 28,
                "offset": 97,
                "words": 2
            },
            <...>
    },
    "clock_region": <CLOCK_REGION>,
    "grid_x": <GRID_X>,
    "grid_y": <GRID_Y>,
    "pin_functions": {
        "<PIN_NAME">: "<PIN_FUNCTION>",
        <...>
    },
    "prohibited_sites": [
        "<SITE_TYPE>",
        <...>
    ],
    "sites": {
        "<SITE_NAME>": <SITE_TYPE>,
        <...>
    },
    "type": "INT_R"
}

The <TILE_NAME> indicates the name of the tile described in the entry. The naming convention matches Vivado.

Each tile entry in the file has the following fields:

• "bits" - contains the data related to tile configuration over the <CONFIGURATION_BUS>. There are three types of the configuration buses in 7-Series FPGAs: CLB_IO_CLK, BLOCK_RAM and CFG_CLB. Every <CONFIGURATION_BUS> has the following fields:

  • baseaddr - Basic address of the configuration frame. Every configuration frame consist of 101 of 32bit words. Note that a single frame usually configures a bunch of tiles connected to the single configuration bus.

  • "frames" - Number of frames that can configure the tile.

  • offset - How many words of offset is present in the frame before the first word that configures the tile.

  • words - How many 32bit words configure the tile.

• clock_region - indicates to which clock region the tile belongs to.

• grid_x - tile column, increasing right

• grid_y - tile row, increasing down

• pin_functions - indicates the special functions of the tile pins. Usually it is related to IOB blocks and indicates i.e. differential output pins.

• prohibited_sites - Indicates which site types cannot be used in the tile

• sites - dictionary which contains information about the sites which can be found inside the tile. Every entry in the dictionary contains the following information:

  • "<SITE_NAME>" - The unique name of the site inside the tile.

  • "<SITE_TYPE> - The type of the site

• type - The type of the tile

Examples

"CLBLL_L_X16Y149": {
    "bits": {
        "CLB_IO_CLK": {
            "baseaddr": "0x00020800",
            "frames": 36,
            "offset": 99,
            "words": 2
        }
    },
    "clock_region": "X0Y2",
    "grid_x": 43,
    "grid_y": 1,
    "pin_functions": {},
    "sites": {
        "SLICE_X24Y149": "SLICEL",
        "SLICE_X25Y149": "SLICEL"
    },
    "type": "CLBLL_L"
}

Interpreted as:

• Tile is named CLBLL_L_X16Y149

• Frame base address is 0x00020800

• For each frame, skip the first 99 words loaded into FDRI

• Since it’s 2 FDRI words out of possible 101, it’s the last 2 words

• It spans across 36 different frame loads

• Located in clock region X0Y2

• Located at row 1, column 43

• Contains two sites, both of which are SLICEL

• Is a CLBLL_L type tile

More information about frames and the FPGA configuration can be found in the Configuration chapter. Example of absolute frame address calculation can be found in the mask file chapter.