CLB_RAM Minitest

Purpose

SLICEM RAM testLUT6 => 64 bitsFocus on 64 bit32 probably uses same O5/O6 stuff128 probably uses same MUX stuffWhy isn’t there a 256?

Result

RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
RAM32M 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM
RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM

RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock